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NXP Semiconductors
Table 5. Static characteristics …continued
T amb = ? 40 ° C to +85 ° C, unless otherwise specified.
LPC11C12/C14
Symbol
Parameter
Conditions
Min
Typ [1]
Max
Unit
I OHS
HIGH-level short-circuit V OH = 0 V
[15]
-
? 45
mA
output current
I OLS
LOW-level short-circuit
V OL = V DD
[15]
-
50
mA
output current
I pd
I pu
pull-down current
pull-up current
V I = 5 V
V I = 0 V
10
? 15
50
? 50
150
? 85
μ A
μ A
2.0 V ≤ V DD ≤ 3.6 V
1.8 V ≤ V DD < 2.0 V
V DD < V I < 5 V
? 10
0
? 50
0
? 85
0
μ A
μ A
I 2 C-bus pins (PIO0_4 and PIO0_5)
V IH
HIGH-level input
0.7V DD
-
-
V
voltage
V IL
V hys
LOW-level input voltage
hysteresis voltage
-
-
-
0.5V DD
0.3V DD
-
V
V
I OL
LOW-level output
V OL = 0.4 V;
I 2 C-bus
pins
[14]
-
-
mA
current
configured as standard
mode pins
2.0 V ≤ V DD ≤ 3.6 V
1.8 V ≤ V DD < 2.0 V
[14]
-
-
I OL
LOW-level output
V OL = 0.4 V;
I 2 C-bus
pins
[14]
20
-
-
mA
current
configured as Fast-mode
Plus pins
2.0 V ≤ V DD ≤ 3.6 V
1.8 V ≤ V DD < 2.0 V
[14]
16
-
-
I LI
input leakage current
V I = V DD
[16]
2
4
μ A
V I = 5 V
-
10
22
μ A
Oscillator pins
V i(xtal)
V o(xtal)
crystal input voltage
crystal output voltage
? 0.5
? 0.5
1.8
1.8
1.95
1.95
V
V
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
Typical ratings are not guaranteed. The values listed are at room temperature (25 ° C), nominal supply voltages.
T amb = 25 ° C.
I DD measurements were performed with all pins configured as GPIO outputs driven LOW and pull-up resistors disabled.
IRC enabled; system oscillator disabled; system PLL disabled.
Pin CAN_RXD pulled LOW externally.
BOD disabled.
All peripherals disabled in the AHBCLKCTRL register. Peripheral clocks to UART and SPI0/1 disabled in system configuration block.
IRC disabled; system oscillator enabled; system PLL enabled.
All oscillators and analog blocks turned off in the PDSLEEPCFG register; PDSLEEPCFG = 0xFFFF FDFF.
[10] WAKEUP pin pulled HIGH externally.
[11] Including voltage on outputs in 3-state mode.
[12] V DD supply voltage must be present.
[13] 3-state outputs go into 3-state mode in Deep power-down mode.
[14] Accounts for 100 mV voltage drop in all supply lines.
LPC11C12_C14_0
Preliminary data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 00.05 — 23 April 2010
? NXP B.V. 2010. All rights reserved.
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